View AS7C1026A-10JC_665708.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

January 2001 Advance Information
(R)
AS7C1026A AS7C31026A
5V/3.3V 64K X 16 CMOS SRAM
Features
* AS7C1026A (5V version) * AS7C31026A (3.3V version) * Industrial and commercial versions * Organization: 65,536 words x 16 bits * Center power and ground pins for low noise * High speed
- 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time
* Latest 6T 0.25u CMOS technology * 2.0V data retention * Easy memory expansion with CE, OE inputs * TTL-compatible, three-state I/O * JEDEC standard packaging
- 44-pin 400 mil SOJ - 44-pin 400 mil TSOP II - 48-ball 6 mm x 8 mm CSP mBGA
* Low power consumption: ACTIVE
- 660 mW (AS7C1026A) / max @ 10 ns - 324 mW (AS7C31026A) / max @ 10 ns
* ESD protection 2000 volts * Latch-up current 200 mA
* Low power consumption: STANDBY
- 55 mW (AS7C1026A) / max CMOS I/O - 36 mW (AS7C31026A) / max CMOS I/O
Logic block diagram
A0 A2 A3 A4 A5 A6 A7 I/O0-I/O7 I/O8-I/O15
Pin arrangement
44-Pin SOJ, TSOP II (400 mil) VCC A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
48-CSP mini Ball-Grid-Array Package
Row decoder
A1
64K x 16 Array
GND
I/O buffer
Control circuit Column decoder
A8 A9 A10 A11 A12 A13 A14 A15
WE
1 2 3 OE A0 A LB B I/O8 UB A3 C I/O9 I/O10 A5 D VSS I/O11 NC E VDD I/O12 NC F I/O14 I/O13 A14 G I/O15 NC A12 H NC A8 A9
4 A1 A4 A6 A7 NC A15 A13 A10
5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6 NC I/O0 I/O2 VDD VSS I/O6 I/O7 NC
UB OE LB CE
Selection guide
AS7C1026A-10 AS7C31026A-10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C1026A-12 AS7C31026A-12 AS7C1026A-15 AS7C31026A-15 AS7C1026A-20 AS7C31026A-20 Unit
10 3 120 90 10 10 AS7C1026A AS7C31026A AS7C1026A AS7C31026A
AS7C1026A AS7C31026A
12 3 110 80 10 10
15 4 100 80 10 10
20 5 100 80 15 15
ns ns mA mA mA mA
2/6/01; V.0.9
Alliance Semiconductor
P. 1 of 9
Copyright (c) Alliance Semiconductor. All rights reserved.
(R)
AS7C1026A AS7C31026A
Functional description
The AS7C1026A and AS7C31026A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high-performance applications. When CE is high the devices enter standby mode. The AS7C1026A is guaranteed not to exceed 55 mW power consumption in CMOS standby mode. The devices also offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0-I/O7, and UB controls the higher bits, I/O8-I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026A) or 3.3V supply (AS7C31026A). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm x 6 mm.
Absolute maximum ratings
Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) AS7C1026A AS7C31026A Both Both Both Both Both Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 -0.50 - -65 -55 - Max +7.0 +5.0 VCC +0.50 1.0 +150 +125 20 Unit V V V W C C mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE H L L L L L L L L WE X H H H L L L H X OE X L L L X X X H X LB X L H L L L H X H UB X H L L L H L X H I/O0-I/O7 I/O8-I/O15 High Z DOUT High Z DOUT DIN DIN High Z High Z High Z High Z DOUT DOUT DIN High Z DIN High Z Mode Standby (ISB), ISBI) Read I/O0-I/O7 (ICC) Read I/O8-I/O15 (ICC) Read I/O0-I/O15 (ICC) Write I/O0-I/O15 (ICC) Write I/O0-I/O7 (ICC) Write I/O8-I/O15 (ICC) Output disable (ICC)
Key: H = High, L = Low, X = don't care.
2/6/01; V.0.9
Alliance Semiconductor
P. 2 of 9
(R)
AS7C1026A AS7C31026A
Recommended operating conditions
Parameter Supply voltage Device AS7C1026A AS7C31026A AS7C1026A AS7C31026A Both commercial industrial Symbol VCC VCC VIH VIH VIL TA TA Min 4.5 3.0 2.2 2.0 -0.5 0 -40 Nominal 5.0 3.3 - - - - - Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85 Unit V V V V V o C oC
Input voltage
Ambient operating temperature
VIL min. = -3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
-10 Parameter
Input leakage current Output leakage current Operating power supply current
-12
-15
-20 Min Max Unit
- 1 A
Sym
| ILI | | ILO |
Test conditions
VCC = Max VIN = GND to VCC VCC = Max CE = VIH, VOUT = GND to VCC VCC = Max, CE VIL outputs open, f = fMax = 1/tRC VCC = Max, CE VIL, outputs open, f = fMax = 1/tRC VCC = Max, CE VCC-0.2V, VIN GND + 0.2V or VIN VCC-0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min
Device
Both
Min Max Min Max Min Max
- 1 - 1 - 1
Both AS7C1026A AS7C31026A AS7C1026A AS7C31026A AS7C1026A AS7C31026A AS7C1026A AS7C31026A AS7C1026A AS7C31026A
- - - - - - - - 2.4
1 120 90 30 30 10 10 0.4 -
- - - - - - - - 2.4
1 110 80 25 25 10 10 0.4 -
- - - - - - - - 2.4
1 100 80 20 20 10 10 0.4 -
- - - - - - - - 2.4
1 100 80 20 20 15 15 0.4 -
A mA mA mA
ICC
Standby power supply current
ISB
ISB1 VOL VOH
mA V V
Output voltage Data retention current
ICCDR
VCC = 2.0V CE VCC-0.2V VIN VCC-0.2V or VIN 0.2V
1 1
1 1
1 1
5 5
mA mA
Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)2
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE, LB, UB I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
2/6/01; V.0.9
Alliance Semiconductor
P. 3 of 9
(R)
AS7C1026A AS7C31026A
Read cycle (over the operating range)3,9
-10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE Low to output in low Z CE High to output in high Z OE Low to output in low Z Byte select access time Byte select Low to low Z Byte select High to high Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tBA tBLZ tBHZ tOHZ tPU tPD Min 10 - - - 2 0 - 0 - 0 - - 0 - Max - 10 10 3 - - 3 - 3 - 5 3 - 10 12 - - - 3 0 - 0 - 0 - - 0 - -12 Min Max - 12 12 3 - - 3 - 3 - 6 3 - 12 15 - - - 3 0 - 0 - 0 - - 0 - -15 Min Max - 15 15 4 - - 4 - 4 - 6 4 - 15 20 - - - 3 0 - 0 - 0 - - 0 - -20 Min Max Unit - 20 20 5 - - 5 - 5 - 8 5 - 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 4, 5 4, 5 5 4, 5 4, 5 4, 5 3 3 Notes
Key to switching waveforms
Rising input Falling input Undefined output/don't care
Read waveform 1 (address controlled)3,6,7,9
tRC Address DataOUT tOH Previous data valid tAA Data valid tOH
Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
tRC Address tAA OE tOLZ CE tLZ LB, UB tBLZ DataIN tBA Data valid tBHZ tACE tOHZ tHZ tOE tOH
2/6/01; V.0.9
Alliance Semiconductor
P. 4 of 9
(R)
AS7C1026A AS7C31026A
Write cycle (over the operating range) 11
-10 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select low to end of write tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW tBW 10 8 8 0 7 0 5 0 - 1 8 - - - - - - - - 6 - - -12 12 10 9 0 8 0 6 0 - 1 10 - - - - - - - - 6 - - 15 12 10 0 9 0 8 0 - 1 12 -15 - - - - - - - - 6 - - -20 Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 Notes 20 12 12 0 12 0 10 0 - 2 12 - - - - - - - - 8 - - Symbol Min Max Min Max Min Max Min Max
Write waveform 1 (WE controlled)10,11
tWC Address tCW CE tBW LB, UB tAS WE tDW DataIN tWZ DataOUT Data undefined Data valid tOW high Z tWC Address tAS CE tCW tAW tBW LB, UB tWP WE tDW DataIN tCLZ DataOUT 2/6/01; V.0.9 high Z tWZ Data undefined high Z P. 5 of 9 Data valid tOW tDH tWR tDH tAW tWP tWR
Write waveform 2 (CE controlled)10,11
Alliance Semiconductor
AS7C1026A AS7C31026A
(R)
Data retention characteristics (over the operating range)
Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR |ILI| VCC = 2.0V CE VCC-0.2V VIN VCC-0.2V or VIN 0.2V Test conditions Min 2.0 - 0 tRC - Max - 1 - - 1 Unit V ma ns ns A
Data retention waveform
Data retention mode VCC VCC tCDR CE VIH VDR VIH VDR 2.0V VCC tR
AC test conditions
- - - - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V.
+3.0V GND DOUT 90% 10% 2 ns 90% 10% 255W C(14) Thevenin Equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V 480W DOUT 255W C(14) +3.3V 320W
Figure A: Input pulse
GND Figure B: 5V Output load
GND Figure C: 3.3V Output load
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C=30pF, except all high Z and low Z parameters where C=5pF.
2/6/01
Alliance Semiconductor
P. 6 of 9
(R)
AS7C1026A AS7C31026A
Package dimensions
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
c
44-pin TSOP II Min (mm)
Max (mm)
44-pin TSOP II
E He
A A1 A2 0.05 0.95
0.30
1.2 1.05 0.45 18.54 10.29 11.96 0.60
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
b c D
D l 0-5 A1 b e
0.127 (typical) 18.28
10.03
A
A2
E He e l
11.56 0.40
0.80 (typical)
D e
44-pin SOJ
E1 E2
Pin 1
B A2 A A1 b c
Seating Plane
E2
A A1 A2 B b c D E E1 E2 e
44-pin SOJ 400 mil Min (in) Max (in) 0.128 0.148 0.025 - 0.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.120 1.130 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM
2/6/01; V.0.9
Alliance Semiconductor
P. 7 of 9
AS7C1026A AS7C31026A
(R)
48-ball FBGA Bottom View 6 5 4 3 2 1 Ball A1 Top View Ball #A1 index
A B C D C1 F G H J
*
SRAM DIE
C
Elastomer A B1 B
*pin 1 indicator will show as engraved circle and/or Inc. trade mark
Side View E2 E Detail View A D E2 E Die E1 Die 0.3/Tp Y
Minimum A B B1 C C1 D E E1 E2 Y - 5.90 - 7.90 - - - - 0.22 -
Typical 0.75 8.00 3.75 8.00 5.25 0.35 - 0.68 0.25 -
Maximum - 8.10 - 8.10 - - 1.20 - 0.27 0.08
Notes 1 Bump counts: 48 (8 row x 6 column). 2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3 Units: millimeters. 4 All tolerance are +/- 0.050 unless otherwise specified. 5 Typ: typical. 6 Y is coplanarity: 0.08 (max).
2/6/01
Alliance Semiconductor
P. 8 of 9
(R)
AS7C1026A AS7C31026A
Ordering codes
Package \ Access time Plastic SOJ, 400 mil Volt/Temp 5V commercial 5V industrial 5V commercial TSOP II, 18.4x10.2 mm 3.3V industrial 5V commercial CSP BGA, 8x6 mm 3.3V industrial 10 ns AS7C1026A-10JC AS7C1026A-10JI AS7C1026A-10TC AS7C31026A-10TI AS7C1026A-10BC AS7C31026A-10BI 12 ns AS7C1026A-12JC AS7C1026A-12JI AS7C31026A-12JC AS7C1026A-12TC AS7C31026A-12TC AS7C31026A-12TI AS7C1026A-12BC AS7C31026A-12BC AS7C31026A-12BI 15 ns AS7C1026A-15JC AS7C1026A-15JI AS7C31026A-15JC AS7C1026A-15TC AS7C31026A-15TC AS7C31026A-15TI AS7C1026A-15BC AS7C31026A-15BC AS7C31026A-15BI 20 ns AS7C1026A-20JC AS7C1026A-20JI AS7C31026A-20JC AS7C1026A-20TC AS7C31026A-20TC AS7C31026A-20TI AS7C1026A-20BC AS7C31026A-20BC AS7C31026A-20BI
3.3V commercial AS7C31026A-10JC 3.3V commercial AS7C31026A-10TC
3.3V commercial AS7C31026A-10BC
Part numbering system
AS7C SRAM prefix X Blank=5V CMOS 3=3.3V CMOS 1026 -XX X Package: J=SOJ 400 mil T=TSOP type 2, 18.4 x 10.2 mm B=CSP BGA, 8 x 6 mm C Temperature range, C= Commercial: 0 C to 70 C I= Industrial: -40 C to 85 C Device Access number time
2/6/01; V.0.9
Alliance Semiconductor
P. 9 of 9
(c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

▲Up To Search▲

Price & Availability of AS7C1026A-10JC

	To Download AS7C1026A-10JC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .